1. Field of the Invention
The present invention relates to a method of designing a circuit board, and, more particularly, it relates to an improvement of the method of designing a circuit board applied to an electronic equipment, by computer-aided design (CAD).
2. Description of the Related Art
An electronic equipment includes a semiconductor device itself such a semiconductor chip and/or other electrical/electronic elements or a circuit board having an electronic device mounted thereon.
In order to meet the recent requirements for reducing the size and weight of the electronic equipment, the electronic device and the circuit board forming the electronic equipment is designed to be smaller in size and higher in density.
A high density circuit board is designed by a computer aided design (CAD). Incidentally, the circuit board is also named as a printed board, which is called as a circuit board here.
In the design of a circuit board by CAD, the board covered is formed with a “rats nest”. This “rats nest” is used as road signs for laying conductor lines (for example, see Japanese Unexamined Patent Publication (Kokai) Nos. 4-34951, 9-91318, 10-171856, and 2003-345844).
For example, as shown in FIG. 18, at step S100, a semiconductor device (electronic device) is drawn. Next, at step S101, pads to which terminals of the electronic device are to be connected (in the case of wire bonding, bonding pads, while in the case of flip-chip, flip-chip connection pads) and external connection terminals are drawn.
The external connection terminals are comprised of for example ball lands to which solder balls are mounted. The conductor lines include vias passing through the circuit board and via lands at the two ends of the vias.
Next, at step S102, the electronic devices are provisionally placed (for “floor plan”) at a designated region of the circuit board (region corresponding to external shape of circuit board).
At step S103, the pads to which the terminals of the electronic devices are connected and the external connection terminals are connected by straight lines, and the pads to which the terminals of a plurality of electronic devices are connected are connected by straight lines. This group of straight lines is called a “rats nest” and serves as road signs for laying conductor lines.
Suitably thereafter, at step S104, the density of the rats nest is confirmed.
A dense region of the rats nest also has dense conductor lines.
Therefore, with this alone, there is a possibility that the laying of conductor lines may become difficult. Therefore, the rats nest is preferably as sparse as possible.
Accordingly, when there is a region with a high density of the rats nest (NO), the routine returns to step S102, where the positions of the electronic devices themselves are moved so that the rats nest becomes sparse (correction of floor plan).
When the density of the rats nest is not so high (YES), the routine proceeds to step S105.
After improving the rats nest in this way, the conductor lines are laid using this rats nest as road signs.
Next, at step S106, whether the arrangement and the laying of the conductor lines is possible or impossible is confirmed or checked. When NO, the routine returns to step S102, where the floor plan is redone.
When YES, the drawing of the circuit board is completed at step S107.
This method of designing the circuit board of the related art can be an effective means for the design of a circuit board with extra space for mounting parts, that is, a relatively large circuit board such as a mother board of a PC etc.
However, in the design of a circuit board with poor extra space for mounting parts, for example, a mother board of a mobile phone or for example a relatively small circuit board such as an interposer used for configuring a System In Package (SIP), there are limits to the space for moving the semiconductor devices to be mounted, so sometimes a dead end is reached with the related art in which the floor plan is repeatedly redone.
Further, in the case where the conductor lines are laid and such a result is discovered that it is impossible to lay all the conductor lines when reaching the final state of the designing process, the routine returns to the initial floor plan, and the arrangement of semiconductor devices is changed, the rats nest is formed, then the conductor lines are laid again.
Therefore, the number of steps in the design process becomes extremely large, the design period is increased, and therefore a large amount of time is required for development of electronic equipment.
In this way, the increase in the development time of a circuit board becomes a major obstacle in development of electronic equipment with short product cycles.